BURIED WORDLINE PDF

Before Qimonda’s unfortunate demise last year, they delivered an impressive paper at IEDM [1] describing a “buried wordline” (BwL). Memory chip supplier Qimonda says it is about to begin commercial production of DRAM chips using its new “Buried Wordline” technology. Provided are a semiconductor device having a buried word line structure in which a gate electrode and a word line may be buried within a substrate to reduce.

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The trench may have a width within a range of about 10 to about nm. In example embodiments, the gate insulating layer may be a thermal oxide layer formed by thermal oxidation.

‘Buried Wordline’ DRAM becomes reality

The semiconductor device of claim 1further comprising: Unlike a polysilicon gate in a conventional DRAM, a word line having 0. When using the atomic layer deposition method using SiH 4 gas or Si 2 H 6 gas, it may be more difficult to form a continuous layer having a thickness of about 5 nm.

The trench may be formed so as to have a width within a range of about 10 to about nm, for example, below 50 nm. Example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

The upper wordlins word line may be formed of any one of tungsten Waluminum Alcupper Cumolybdenum Motitanium Ti worcline, tantalum Taand ruthenium Ruor a combination thereof. In example embodiments, the lower buried word line may include polysilicon. Accordingly, when the gate electrode layer includes polysilicon and is formed to a thickness of about 5 nm, woedline atomic layer deposition may be carried out using the Si 3 H 8 gas.

Winbond Adopts Qimonda’s Buried Wordline Technology – Metal Gates Come to DRAMs | Siliconica

According to example embodiments, a semiconductor biried having a bruied word line structure may comprise a semiconductor substrate defined by a device isolation layer and comprising an active region in which a trench for forming one or more recess channels are formed.

The buried word line may be formed by forming a word line layer on the substrate so as to bury the trench In example embodiments, the upper buried word line may include a silicide.

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Unless otherwise defined, all terms including technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which example embodiments belong. The top surface of the capping layer may be formed so as to not protrude beyond the surface of the substrate.

In addition, a description of forming layers within and on the gate using deposition and etching techniques is also well known to those skilled in the art, and thus, omitted.

6F2 buried wordline DRAM cell for 40nm and beyond

Description of Related Art Recently, there has been increasing research on the buried word line cell array transistor BCAT in which a word line WL may be buried below the surface of a semiconductor substrate using a metal and not a polysilicon as a gate electrode in the structure of a conventional recess channel array transistor RCAT.

One or more recess channels may be formed, and accordingly a plurality of trenches may be formed within the active region defined by the device isolation layer In order to form the trencha buffer insulating layer e. Example embodiments also provide wodline method of fabricating a semiconductor device having the buried word line structure as described above.

Therefore, it is to be understood that the foregoing is illustrative of wirdline embodiments and is not to be construed as limited to the specific embodiments disclosed, and that modifications to the disclosed embodiments, as well as other embodiments, are intended to be included within the scope of the appended claims. Therefore, in the above structure, the semiconductor device having a height corresponding to the protruded portion of the metal gate electrode 20 is formed.

It will be understood that, although the terms buriev, second, third etc. Semiconductor device including a field effect transistor and method of forming thereof. Furthermore, because the lower buried word line may be formed of polysilicon, a reduction of the aspect ratio is obtained. However, this is merely illustrative and thus, the upper buried word line is not limited to these metals. Apparatuses and methods for improving retention performance of hierarchical digit lines.

In example embodiments, the gate electrode layer may be formed using a chemical vapor deposition CVD or an atomic layer buriwd ALD method. Reference will now be made in detail to example embodiments, examples of which are illustrated in the accompanying drawings.

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Therefore, in order to form the continuous polysilicon layer having a width of about 5 nm, Si 3 H 8 gas may be used. Capacitor with electrodes made of ruthenium and method for patterning layers made of ruthenium or ruthenium IV oxide. In example embodiments, the trench may be formed to have a width within a range of about 10 to about nm. In addition, the diffusion length may be shorter in comparison to the buried word line being formed only of silicide.

‘Buried Wordline’ DRAM becomes reality | Electronics News

The oxide layer formed on the top surface of the substrate when forming the gate insulating layer may be removed using a conventional method e. The semiconductor device having a nuried word line structure may further comprise a gate insulating layer on the surface of the trench, a gate electrode layer on the surface of the gate insulating layer, and a buried word line burying the trench on the surface of the gate electrode layer.

Thus, the top surfaces of the gate electrode layer and the gate insulating layer may also be recessed within the substrate and may be formed such that the capping buriied caps simultaneously the recessed regions of the gate insulating layer and the gate electrode layer and the recessed region of the buried word line The gate insulating layer may be a thermal oxide layer formed by thermal oxidation.

The word line layer may then be polished using a chemical mechanical polishing CMP method and etched back using a dry etch process to expose the surface of the substrate Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or bhried without departing from the teachings of example embodiments.

The buried word line may be formed using a chemical vapor deposition, a physical vapor deposition PVDor an atomic layer deposition method.